1. Field of the Invention
This invention relates to the production of thinned semiconductor wafers which are made from thick (100 μm to 700 μm) wafers that are thinned from the backside (or potentially front side) only in selected regions.
2. Description of the Previously Published Art
There are several companies that are attempting to make Insulated Gate Bipolar Transistors (IGBTs) that have a semiconductor wafer thickness between 100 μm and 200 μm. The main problems in making these devices in a manufacturing environment are wafer warpage, wafer breakage, and difficulty of using automated equipment.
There are devices where it would be desirable to have power devices with a total thickness of 25 μm. These power devices include fast recovery 200V PN junction rectifiers and MOSFETs. However, semiconductor wafers that are thinned to 25 μm would be extremely difficult to manufacture.
A new technology of Deep Reactive Ion Etch has been recently developed. Semiconductor processing tools utilizing this technology can achieve etching rates of 10 μm per minute with trench aspect ratio approaching 100:1. Thus, deep, relatively narrow (5 μm–20 μm wide) trenches can be etched entirely through the thickness of a semiconductor wager. This technology has been used for microelectromechanical systems (MEMS) such as microsensors and microactuators microactuators. However, for the application to power devices as described in this disclosure, only a partial etch through the thickness of the wafer is used.
3. Objects of the Invention
It is an object of this invention to provide a process for producing vertical conducting power devices where the semiconductor wafers have been thinned to semiconductor thickness ranging from 10 μm thick to 200 μm.
It is a further object of this invention to provide vertical conducting power devices having significantly reduced substrate resistance which provides improved forward voltage.
It is a further object of this invention to provide vertical conducting power devices having significantly reduced thermal impedance of the substrate so as to obtain acceptable operating temperatures for high power devices.
It is a further object of this invention to provide vertical conducting power devices having reduced fabrication cost through the use of low doping concentration float zone wafers in one embodiment rather using the expensive growth of thick epitaxial layers on heavily-doped substrates.
It is a further object of this invention to provide vertical conducting power devices having low doping concentration float zone wafers so that P and N doping regions can be defined at the backside of the wafer to implement specialized structures such as anode shorts, cathode shorts, and defined emitter area.
It is a further object of this invention to provide vertical conducting power devices having low doping concentration float zone wafers so that localized lifetime killing near the backside interface of the device can also be obtained using high energy proton and He implants in thinned semiconductor devices.
It is a further object of this invention to provide vertical conducting power devices having reduced wafer warpage and wafer breakage in the manufacturing environment and a compatibility with automated handling.
These and further objects of the invention will become apparent as the description of the invention proceeds.